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AK8180C ms1305 - e - 00 may - 2011 - 1 - features 12 lvcmos outputs selectable lvcmos and lvpecl in puts 2.5v or 3.3v power supply clock frequency up to 3 50mhz o utput - to - output skew : 15 0ps max synchronous output stop in logic state high - i mpedance output control d rive up to 24 series terminated clock lines operating temperature range: - 4 0 to +85 package: 32 - pin l qfp (pb free) pin compatible with mpc9448 description the AK8180C is a member of akm lvcmos clock fanout buffer family designe d for telecom, networking and computer applications , requiring a ra nge of clocks with high performance and low skew . the AK8180C distributes 12 buffered clocks up to 350mhz . the 12 outputs can drive terminated 50 ? clock lines. the clk_stop control allows the output signal to start and stop only in a logic low state. the oe control sets the outputs to high - impedance mode. AK8180C are derived f r o m akm long - term - experienced clock devic e technology , and enable clock output to perform low skew . the AK8180C is ava ilable in a 7mm x 7mm 32 - pin lqfp pa ckage. block diagram 2.5v, 3.3v lvcmos 1:12 clock fanout buffer AK8180C
AK8180C may - 2011 ms1305 - e - 00 - 2 - pin d escription s v d d g n d q 4 v d d q 5 g n d q 6 q 7 v d d c l k _ s e l c c l k p c l k p p c l k n o e g n d c l k _ s t o p p ackage: 32 - pin lqfp (top view) pin no. pin name pin type pullup /down description 1 clk_sel in -- clock input select 2 cclk in pu clock input (lvcmos) 3 pclkp in pu clock input (lvpecl) 4 pclkn in pu/pd clock input (lvpecl) 5 clk_stop in pu clock output disable (active low) 6 oe in pu clock output enable (disable=high impedance ) 7 vdd -- -- power supply 8, gnd -- -- ground 9 q11 out -- clock output 10 vdd -- -- power supply 11 q10 out -- clock output 12 gnd -- - - ground pu: pull up pd: pull down (continued on next page)
AK8180C ms1305 - e - 00 may - 2011 - 3 - pin no. pin name pin type pullup /down description 13 q9 out -- clock output 14 vdd -- -- power supply 15 q8 out -- clock output 16 gnd -- -- ground 17 q7 out -- clock outpu t 1 8 vdd -- -- power supply 1 9 q6 out -- clock output 20 gnd -- -- ground 21 q5 out -- clock output 22 vdd -- -- power supply 23 q4 out -- clock output 24 gnd -- -- ground 25 q3 out -- clock output 26 vdd -- -- power supply 27 q2 o ut -- clock output 28 gnd -- -- ground 29 q1 out -- clock output 30 vdd -- -- power supply 31 q0 out -- clock output 32 gnd -- -- ground ordering information part number marking shipping packaging package temperature range AK8180C ak 81 80 c tape and reel 32 - pin lqfp - 4 0 to 85
AK8180C may - 2011 ms1305 - e - 00 - 4 - absolute maximum rating over operating free - air temperature range unless otherwise noted (1) items s ymbol ratings unit s upply v oltage vdd - 0.3 to 4.6 v input voltage vin gnd - 0.3 to vdd+0.3 v input c urrent (any pins except supplies) i in 1 0 ma storage temperature tstg - 5 5 to 130 ? c note (1) stress beyond those listed under absolute m ax imum r atings may cause perman ent damage to the device. these are stress ratings only. f unctional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute - maximum - rating conditions for extended periods may affect device reliability. electrical par ameters are guaranteed only o ver the recommended operating temperature range. this device is manufactured on a cmos process, therefore, generically susceptible to damage by excessive static voltage. failure to observe proper handling and in stallation procedures can cause damage . akm recommends that this device is handled with appropriate precautions. recommended operation condition s parameter s ymbol conditions m in typ m ax unit operating t emperature ta - 4 0 85 ? c supply voltage (1) vdd vdd ? 5% 2.375 2.5 2.625 v 3. 135 3. 3 3. 465 (1) power of 2.5v or 3.3v require s to be supplied from a single source. a decoupling capacitor of 0. 0 1 ? f for power supply line should be locat ed close to each vdd pin. general specification parameter s ymbol conditions m in typ m ax unit o utput termination voltage vtt vdd/2 v esd protection 1 mm machine model 200 v esd protection 2 hbm human body model 2000 v latch - up immunity lu 200 ma power dissipation capacitance p er output 10 pf input capacitance 4.0 pf esd sensitive device
AK8180C ms1305 - e - 00 may - 2011 - 5 - power supply current <3.3v> vdd = 3.3v ? 5% , ta: - 40 to +85 parameter s ymbol conditions m in typ m ax unit full operation (1) idd1 cclk0=350mhz clk_sel=l 155 175 ma quiescent state ( 1 ) (2) idd2 1.0 2.0 ma ( 1 ) the outputs have no loads. (2) all inputs are in default state by the internal pull up/down resis ters. dc characteristics <3.3v> all specifications at vdd = 3.3 v ? 5% , ta: - 4 0 to +85 , unless otherwise noted parameter symbol conditions min typ max unit high l evel i nput v oltage v ih lvcmos 2.0 vdd+0.3 v low l evel i nput v oltage v il lvcmos - 0.3 0. 8 v peak - to - peak input voltage vpp lvpecl 250 mv common mode range (1 ) vcmr lcpecl 1.1 vdd - 0.6 v input c urrent (2 ) i l 1 vin= gnd or vdd - 300 + 3 00 a high level o utput voltage v oh i oh = - 2 4 ma (3 ) 2.4 v low l evel o utput voltage v ol i o l = + 2 4 ma (3 ) i o l = + 12 ma 0. 55 0.30 v output impedance 17 ? (1) vcmr(d c) is the crosspoint of the dif ferential input signal. functional operation is obtained when the crosspoint is within the vcmr range and the i nput swing lies within the vpp(d c) specification. (2) i nput pull - u p / pull down resisto rs influence input current. (3) the AK8180C is capable of driving 50 ? transmission lines of the incident edge. each output drives one 50 ? parallel terminated transmission line to a termination voltage of vtt . alternatively, the device dr ives up to two 50 ? series terminated transmission lines (for vdd=3.3v) or one 50 ? seri es terminated transmission line (for vdd=2.5v) . ac characteristics <3.3v> ( 1 ) all spec ifications at vdd = 3.3v ? 5%, ta: - 40 to +85 , unless otherwise noted parameter symbo l conditions min typ max unit input f requency f in pin: cclk , pclkp/n 0 3 50 mhz input pulse width t p w in pin: cclk , pclkp/n 1.4 n s peak - to - peak input voltage vpp pin: pclkp/n 400 1000 mv common mode range (2 ) vcmr pin: pclkp/n 1.3 vdd - 0.8 input ri se/fall time (3 ) t rin ,t fout pin: cclk 0.8 to 2.0v 1.0 n s output frequency f out pin: q0 - 11 0 3 50 mhz propagation delay t plh t phl p clk to any q cclk to any q 1.0 0.8 1.8 1.6 3.0 2.8 n s output disable time t plz , t phz 1 1 n s output enable time t pzl , t pzh 1 1 n s setup time t s cclk to clk_stop pclk to clk_stop 0.0 0.0 ns hold time t h cclk to clk_stop pclk to clk_stop 1.0 1.5 ns output - to - output skew t sk(o) 150 ps device - to - device sk ew t skpp 2.0 ns output pulse skew (4 ) t sk(p) cclk pclk 300 400 ps output duty cycle dc out f out < 170mhz dc ref =50% 45 50 55 % output rise/fall time t r , t f 0.55 to 2.4v 0.1 1.0 n s
AK8180C may - 2011 ms1305 - e - 00 - 6 - (1) ac characteristics apply for parallel output termination of 50 ? to vtt . (2) vcmr(ac) is the crosspoint of the differential input signal. normal ac operation is obtained when the crosspoint is within the vcmr range and the input swing lies within the vpp(ac) specification. violation of vcmr or vpp impacts t plh /phl and t skd . (3) violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, devi ce - to - device skew, input pulse width, output duty cycle and maximum frequency specifications . (4) output pulse skew t sko is the absolute difference of the propagation delay times : | t plh - t p hl |. power supply current <2.5v> vdd= 2.5 v ? 5%, ta: - 40 to +85 parameter s ymbol conditions m in typ m ax unit full operation (1) idd2.5 - 1 2.5v ? 5%, cclk0=350mhz clk_sel=l 115 134 ma qui escent state ( 1 ) (2) idd2.5 - 2 0.7 1.3 ma ( 1 ) the outputs have no loads. (2) all inputs are in default state by the internal pull up/down resisters. dc characteristics <2.5v> all specifications at vdd= 2.5v ? 5%, ta: - 40 to +85 , unless otherwise note d parameter symbol conditions min typ max unit high l evel i nput v oltage v ih lvcmos 1.7 vdd+0.3 v low l evel i nput v oltage v il lvcmos - 0.3 0. 7 v peak - to - peak input voltage vpp lvpecl 250 mv common mode range (1 ) vcmr lv pecl 1.0 vdd - 0.7 v input c ur rent (2 ) i l 1 vin=gnd or vdd - 300 + 300 a high level o utput voltage v oh i oh = - 15 ma (3 ) 1.8 v low l evel o utput voltage v ol i o l = + 15 ma (3 ) 0. 6 v output impedance 19 ? (1) vcmr(dc) is the crosspoint of the differential input signal. functional operation is obtained when the crosspoint is w ithin the vcmr range and the input swing lies within the vpp(dc) specification. (2) input pull - up / pull down resistors influence input current. (3) the AK8180C is capable of driving 50 ? transmission lines of the incident edge. each output drives one 50 ? parall el terminated transmission line to a termination voltage of vtt . alternatively, the device drives up to two 50 ? series terminated transmission lines (for vdd=3.3v) or one 50 ? series terminated transmission lines(for vdd=2.5v). ac characteristics <2.5v> ( 1 ) all specifications at vdd= 2.5 v ? 5%, ta: - 40 to +85 , unless otherwise noted (continued on next page) parameter symbol conditions min typ max unit input f requency f in pin: cclk, pclkp/n 0 350 mhz input pulse width t pwin pin: cclk, pclkp/n 1.4 ns peak - to - peak input voltage vpp pin: pclkp/n 400 1000 mv common mode range (2 ) vcmr pin: pclkp/n 1.2 vdd - 0.8 input rise/fall time (3 ) t rin ,t fout pin: cclk 0.8 to 2.0v 1.0 ns output frequency f out pin: q0 - 11 0 350 mhz propagation delay t plh t phl pclk to any q cclk to any q 1.0 0.9 1.9 1.8 3.7 3.6 n s output disable time t plz , t phz 11 ns output enable time t pzl , t pzh 11 ns
AK8180C ms1305 - e - 00 may - 2011 - 7 - (1) ac characteristics apply for parallel output termination of 50 ? to vtt . (2) vcmr(ac) is the crosspoint of the differential input signal. normal ac operation is obtained wh en the crosspoint is within the vcmr range and the input swing lies within the vpp(ac) specification. violation of vcmr or vpp impacts t plh /phl and t skd . (3) violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation dela y, device - to - device skew, input pulse width, output duty cycle and maximum frequency specifications. (4) output pulse skew t sko is the absolute difference of the propagation delay times:| t plh - t p hl |. figure 1 cclk ac test reference figure 2 pclk ac test reference parameter symbol conditions min typ max unit setup time t s cclk to clk_stop pclk to clk_stop 0.0 0.0 ns hold time t h cclk to clk_stop pclk to clk_stop 1.0 1.5 ns output - to - output skew t sk(o) 150 ps device - to - device skew t skpp 2.7 ns output pulse skew (4 ) t sk(p) cclk pclk 200 300 ps output duty cy cle dc out dc ref =50% 45 50 55 % output rise/fall time t r , t f 0.6 to 1.8 v 0.1 1.0 n s
AK8180C may - 2011 ms1305 - e - 00 - 8 - figure 3 propagation delay test reference figure 4 propagation delay test reference figure 5 output - to - output skew figure 6 outp ut pulse skew test reference figure 7 output duty cycle figure 8 output translation test reference figure 9 setup and hold time test reference
AK8180C ms1305 - e - 00 may - 2011 - 9 - function table the following table shows the inpu t s /output s clock state configured through the control pins . table 1 : control - pin - setting function t able control pin default 0 1 clk_sel 1 p clk differential input selected c clk input selected oe 1 outputs disabled. (high impedanc e ) outputs enabled clk_stop 1 outputs synchronously stopped in logic low state. outputs active application example of clk_stop
AK8180C may - 2011 ms1305 - e - 00 - 10 - package information ? mechanical data 0 b 7 b 0 . 0 5 0 . 1 5 0 . 0 9 0 . 2 0 0 . 20 m 0 . 37 0 . 05 1 8 9 16 17 24 25 32 7 . 00 9 . 00 0 . 20 9 . 0 0 0 . 2 0 7 . 0 0 0 . 80 0 . 60 0 . 10 1 . 6 0 m a x 1 . 3 5 1 . 4 5 s s 0 . 10
AK8180C ms1305 - e - 00 may - 2011 - 11 - ? marking a: #1 pin index b: part number c: date code (7 digits) (1) akm is the brand name of akm ic s. akm and the logo - - are the brand of akm ic s and identify that akm continues to offer t he best choice for high performance mixed - signal solution under this brand. ? rohs complian ce all integrated circuits form asahi kasei m icrodevices corporation (akm) assembled in lead - free packages* are fully c ompliant with rohs. (*) rohs compliant products from akm are identified with pb free letter indication on product label posted on the anti - shield bag and boxes. a b c
AK8180C may - 2011 ms1305 - e - 00 - 12 - important notice ? these products and their specifications are subject to change without notice. when you consider any use or application of these products, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authori zed distributors as to current status of the products. ? descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither i ntended nor authorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by represe ntative director of akm. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containi ng it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear ener gy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. ? it is the responsibility of the buyer or distributor of akm products, who distri butes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harml ess from any and all claims arising from the use of said product in the absence of such notification.

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